Embedded DRAM for metal-insulator-metal (MIM) capacitor structure

ABSTRACT

A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.

BACKGROUND OF THE INVENTION

[0001] (1) Field of the Invention

[0002] The present invention relates to methods of fabricating a metal-insulator-metal capacitor, and more particularly, to methods of forming metal-insulator-metal capacitors for embedded DRAM applications wherein contact etch depth is reduced in the fabrication of an integrated circuit device.

[0003] (2) Description of the Prior Art

[0004] In merging logic circuits and dynamic random access memory (DRAM) arrays on a single chip, compatibility is the primary issue with respect to both design and fabrication. Recently, with the continued decrease in device dimensions, it has become increasingly important to find solutions to problems that are caused by etching high aspect ratio contact openings. The DRAM capacitor's height must be increased in order to meet the high capacitance requirement. Meanwhile, in order to achieve a high dielectric constant for a metal-insulator-metal (MIM) or metal-insulator-silicon (MIS) capacitor, the dielectric material should be deposited at high temperature (of more than about 600° C.) or annealed at high temperature after film deposition. Thus, the capacitor formation must be completed before the copper/low dielectric constant (k) material process. But this limitation will impact contact etching because of device dimension shrinkage. Because of the high capacitance requirement, the height of the capacitor cannot be reduced. However, we can try to improve the contact high aspect ratio etch problem in other ways. U.S. Pat. Nos. 6,096,597 to Tsu et al, 6,329,234B1 to Ma et al, and 6,271,084B1 to Tu et al show MIM capacitor processes. U.S. Pat. No. 6,211,061 to Chen et al teaches a dual damascene process with carbon-based low-k materials.

SUMMARY OF THE INVENTION

[0005] Accordingly, it is a primary object of the invention to provide an effective and very manufacturable process for producing a metal-insulator-metal capacitor in an embedded DRAM process.

[0006] Another object of the present invention is to provide a method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process with reduced contact etch depth.

[0007] In accordance with the objects of this invention, a method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is achieved. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.

[0008] Also in accordance with the objects of this invention, a method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is achieved. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in two twisted trench in a self-aligned copper process. The two twisted trenches are mirror images of each other wherein each capacitor in a first of the two twisted trenches is horizontally aligned with a capacitor in the second of the two twisted trenches to form pairs of capacitors wherein the pairs of capacitors are separated from each other horizontally by a first or a second distance wherein the first distance is greater than the second distance. The capacitors are formed by the following process. A silicon carbide layer is deposited overlying the contact plugs. A low dielectric constant material layer is deposited overlying the silicon carbide layer. A stop layer is deposited overlying the low dielectric constant material layer. A first opening is formed through the stop layer, the low dielectric constant material layer, the silicon carbide layer, and the insulating layer to the node contact plug. A first metal layer is deposited overlying the stop layer and within the first opening. The first opening is filled with a sacrificial layer which is etched back to leave the first metal layer only within the first opening and recessed from the top of the first opening wherein the first metal layer forms a bottom electrode of the capacitor. Thereafter, the sacrificial layer and the stop layer are removed. A twisted trench is formed. A capacitor dielectric layer is deposited overlying the bottom electrode. A second metal layer is deposited overlying the capacitor dielectric layer. A third metal layer is deposited overlying the second metal layer and filling the first opening. The third metal layer, the second metal layer, and the capacitor dielectric layer are polished back to leave these layers only within the first opening wherein the second and third metal layers together form a top electrode of the capacitor. Second openings are etched through the low dielectric constant layer and the silicon carbide layer to the contact plugs. The second opening in the memory area lies between the two twisted trenches and in a horizontal line with one capacitor pair having the first separation distance wherein adjacent capacitor pairs have the second separation distance. The second openings are filled with a fourth metal layer to complete contacts to the contact plugs in the logic area and in the memory area.

[0009] Also in accordance with the objects of the invention, an improved embedded DRAM and capacitor structure device is achieved. Trenched capacitors are formed in two twisted trenches through an insulating layer in a memory area of an integrated circuit wherein the two twisted trenches are mirror images of each other and wherein each capacitor in a first of the two twisted trenches is horizontally aligned with a capacitor in a second of the two twisted trenches to form pairs of capacitors wherein the pairs of capacitors are separated from each other horizontally by a first or a second distance wherein the first distance is greater than the second distance. A bit line contact in the memory area through the insulating layer to a bit line lies between the two twisted trenches and in a horizontal line with one capacitor pair having the first separation distance wherein adjacent capacitor pairs have the second separation distance. First line metal contacts are formed in a logic area of the integrated circuit. The bit line contact and the first line metal contacts are no higher vertically than the trenched capacitors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the following drawings forming a material part of this description, there is shown:

[0011]FIG. 1 is a schematic cross-sectional representation of an embedded DRAM device of the prior art.

[0012]FIGS. 2 through 13, 15A, 15B, 17A, 17B, 19A, 19B, 21A, 21B, 23A, 23B, 24, and 25 are schematic cross-sectional representations of a first preferred embodiment of the present invention.

[0013]FIGS. 14, 16, 18, 20, and 22 are top views of a first preferred embodiment of the present invention.

[0014]FIG. 26 is a top view of a second preferred embodiment of the present invention.

[0015]FIGS. 27A and 27B are schematic cross-sectional representations of a second preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The process of the present invention provides methods for fabricating a metal-insulator-metal (MIM) capacitor in an embedded DRAM process wherein the contact etch is improved.

[0017] Referring now more particularly to FIG. 2, there is shown a partially completed integrated circuit device. The semiconductor substrate 10 is preferably composed of silicon having a (100) crystallographic orientation. Semiconductor device structures are formed in and on the semiconductor substrate. For example, isolation regions such as shallow trench isolation (STI) 12 are formed in the semiconductor substrate to separate active areas. A gate oxide layer 16 is grown or deposited on the substrate surface. A polysilicon layer 18 is deposited over the gate oxide layer, followed by a hard mask layer of silicon oxynitride (SiON) 20, for example. The SiON, polysilicon, and gate oxide layers are patterned to form gate electrodes, as shown in FIG. 2, in both the logic area L and the memory area M.

[0018] Now, as shown in FIG. 3, the hard mask layer is stripped and lightly doped source and drain regions 22 are formed, for example, by ion implantation. Spacers 24 are formed on the sidewalls of the gate electrodes 18 and used as a mask for implanting source/drain regions 26 in the logic area L, as shown in FIG. 4.

[0019] Referring now to FIG. 5, a layer of resist protective oxide (RPO) 30 is conformally deposited over the surface of the substrate. The RPO layer 30 will protect the DRAM area from salicidation. As illustrated in FIG. 6, the RPO layer is removed in the logic area L. Silicide 34 is formed on the gates and source/drain regions in the logic area by a self-aligned salicide process.

[0020] Now, an insulating layer is to be formed over the device structures. For example, as shown in FIG. 7, a first conformal layer of silicon oxynitride 38 is deposited over the device structures. Then a thick insulating layer 40, such as chemically vapor deposited (CVD) silicon dioxide, phosphosilicate glass (PSG), high density plasma oxide, or the like, is deposited over the gate electrodes 18 and then planarized, for example by chemical mechanical polishing (CMP), to obtain a flat surface. The insulating layer 40 should have a thickness of about 3000 Angstroms over the gate electrodes after CMP.

[0021] Referring now to FIG. 8, the thickness of the insulating layer 40 over the gate electrodes is further reduced to be between about 600 and 1400 Angstroms. For example, this may be done by a plasma dry etch back process that is carefully controlled using a time mode etching recipe dependent upon the variation thickness of the CMP step.

[0022] Next, a stop layer 42 is deposited over the insulating layer 40. For example, the stop layer 42 may comprise silicon oxynitride or silicon nitride and have a thickness of between about 300 and 1000 Angstroms. As illustrated in FIG. 9, contact openings are etched through the stop layer 42 and the insulating layers 40, 38, and 30 to the regions 22 that will form the DRAM cell storage nodes. The contact openings are lined with a barrier layer, not shown, which may be titanium and titanium nitride, for example, then filled with a tungsten layer. The tungsten layer is planarized using CMP, for example, to leave tungsten plugs 46.

[0023] Referring now to FIG. 10, a second insulating layer 50 is deposited over the tungsten plugs. This insulating layer may have a thickness of between about 5000 and 15,000 Angstroms. Contact openings are made through the second oxide layer 50, the stop layer 42, and the underlying insulating layers to provide a bit line contact 52 in the memory area M and first metal line contacts 54 in the logic area L. The contact openings are lined with a barrier layer, not shown, which may be titanium and titanium nitride, for example, then filled with a tungsten layer. The tungsten layer is planarized using CMP, for example, to leave tungsten plugs 52 and 54. These contacts are a key feature of the present invention. In the prior art, the contacts are usually opened after the capacitor's formation. However, in the process of the present invention, the contacts are opened prior to formation of the capacitor. Because of this fact, the contact height is reduced. For example, if a 25 fF/cell capacitance is needed, the prior art requires a capacitor height of about 15,000 Angstroms. However, the capacitor of the present invention requires a height of only 12,000 Angstroms while attaining the same capacitance. This great improvement in contact depth is achieved through the unique process and layout of the present invention.

[0024] As illustrated in FIG. 11, a stop layer 60 is deposited over the tungsten plugs 52 and 54 to a thickness of between about 300 and 700 Angstroms. This layer may be silicon nitride or silicon carbide. Now, a low-k material layer 62 is deposited over the SiC layer 60. The low-k material layer may comprise fluorinated silicate glass or undoped silicate glass, for example, and have a thickness of between about 1000 and 5000 Angstroms. A SiON layer 64 is deposited to a thickness of between about 200 and 600 Angstroms overlying the low-k material layer 62.

[0025] Referring now to FIG. 12, openings are etched in the memory area into the dielectric layers with an etch stop at the SiON or SiN layer 42. These openings will form the storage nodes of the capacitor structures of the present invention. Now, a layer such as tantalum nitride or titanium nitride 70 is deposited conformally over the SiON layer 64 and within the storage node openings. The TaN or TiN layer will form the bottom electrode of the capacitor.

[0026] Referring now to FIG. 13, a photoresist layer 72 is coated over the tantalum nitride layer 70 and partially etched back to remove the tantalum nitride layer 70 overlying the SiON layer 64 and to leave the photoresist 72 only within the storage node openings.

[0027]FIG. 14 shows a top view of the capacitor storage node openings 65 after the photoresist 72 and the SiON layer 64 has been stripped. FIG. 15A shows view A-A of FIG. 14. FIG. 15B shows view B-B of FIG. 14.

[0028]FIG. 16 again shows a top view while FIG. 17A shows view A-A of FIG. 16 and FIG. 17B shows view B-B of FIG. 16. A second layer of photoresist 76 is coated over the substrate. Now, another key feature of the invention is to be described. A twist line pattern is formed by photolithography techniques. In the twist line pattern, the window between the capacitors and the contact to be formed later is enlarged. This can be seen along line A-A of FIG. 16 where the openings are farther apart than are the openings above and below these in the drawing. In the twist line pattern are two twisted trenches that are mirror images of each other wherein each capacitor in a first of the two twisted trenches is horizontally aligned with a capacitor in a second of the two twisted trenches to form pairs of capacitors wherein the pairs of capacitors are separated from each other horizontally by a first or a second distance wherein the first distance is greater than the second distance.

[0029] A twist trench is etched as shown in top view in FIG. 16. This etch etches the tantalum nitride layer 70 and low-k material layer 62 with a stop on the silicon nitride layer 60, as shown in FIG. 17B. A cross-sectional view of the twist trench is shown in FIG. 17A.

[0030]FIG. 18 again shows a top view after removal of the photoresist 76. FIG. 19A shows view A-A of FIG. 18 and FIG. 19B shows view B-B of FIG. 18.

[0031] Referring now to the top view of FIG. 20 and the cross-sectional views of FIGS. 21A and 21B, a capacitor dielectric layer 80 is deposited conformally within the openings 65 and over the tantalum nitride layer 70. The capacitor dielectric layer 80 may be tantalum oxide or any other high dielectric constant material and have a thickness of between about 100 and 400 Angstroms. A second tantalum nitride or titanium nitride layer 82 is deposited over the capacitor dielectric layer. This layer 82 will form the top electrode of the capacitor. Preferably, an annealing step is performed at between about 450 and 650° C. Now, a copper layer 84 is deposited over the tantalum nitride layer 82 and filling the storage node openings.

[0032] As shown in FIGS. 22, 23A, and 23B, the copper is planarized by CMP. This completes the capacitor structure. The copper 84 and the tantalum nitride layer 82 form the top electrode of the capacitors.

[0033] Now a capping layer 90 is deposited over the capacitors as shown in FIG. 24. The capping layer 90 may comprise SiON and have a thickness of between about 200 and 600 Angstroms. A photoresist mask 92 is formed over the substrate and via openings are made to the tungsten plugs 52 and 54. The via opening in the memory area lies between the two twisted trenches and in a horizontal line with one capacitor pair having the first separation distance wherein adjacent capacitor pairs have the second separation distance.

[0034] Referring now to FIG. 25, a single damascene process is performed to fill the via openings with a barrier layer such as tantalum nitride 94 and copper layer 96 or 98. CMP planarization completes the first metallization. First line metal contacts 96 are formed in the logic area and bit line contact 98 is formed in the memory area. The bit line will later be formed. The top electrodes 84 shown in FIG. 25 are self-aligned because of the twist line pattern to have an enlarged window between the top electrodes 84 and the bit line contact 98.

[0035]FIGS. 26, 27A, and 27B illustrate a second preferred embodiment of the present invention. In this embodiment, after FIG. 19B, the exposed silicon carbide layer 60 is removed. Additional openings are etched through the insulating layer 50 to the stop layer 42. This provides increased capacitor area as shown in FIG. 27B. Processing continues to form the capacitor dielectric layer 80 and the top electrode 82/84 as described in the first embodiment. The view in FIGS. 26 and 27A is the same in both embodiments.

[0036] The process of the present invention provides a method for forming a MIM capacitor in an embedded DRAM process. The following advantages can be seen. A carefully controlled insulating layer thickness will improve the deep contact etch by reducing high aspect ratio of the contact openings. The contact etch depth is decreased by about 20% which is a great improvement for the contact etch. A twist line top plate electrode formed by a self-aligned copper process enlarges the DRAM cell process window between the bit line and the capacitor. Refer to FIG. 1, illustrating a typical capacitor under bitline (CUB) DRAM of the prior art where contacts 110 are opened after formation of the capacitors 100. A narrow process window exists because of the narrow overlay margin A between the top plate electrode and the contact 110. The process of the present invention has a larger process window because of the self-aligned process. As shown in FIG. 27A, the margin B between the top plate electrode and the contact is much larger than in the prior art.

[0037] Also, referring to FIGS. 26 and 27A, an improved embedded DRAM and capacitor structure device is described. Trenched capacitors 84 are formed in two twisted trenches (FIG. 26) through an insulating layer in a memory area M of an integrated circuit wherein the two twisted trenches are mirror images of each other and wherein each capacitor in a first of the two twisted trenches is horizontally aligned with a capacitor in a second of the two twisted trenches to form pairs of capacitors wherein the pairs of capacitors are separated from each other horizontally by a first or a second distance wherein the first distance is greater than the second distance. A bit line contact 98 in the memory area M through the insulating layer to a metal plug 52 lies between the two twisted trenches and in a horizontal line with one capacitor pair having the first separation distance wherein adjacent capacitor pairs have the second separation distance. First line metal contacts 96 are formed in a logic area L of the integrated circuit. The bit line contact 98 and the first line metal contacts 96 are no higher vertically than the trenched capacitors 84.

[0038] While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention. 

What is claimed is: 1-32. (canceled)
 33. An embedded DRAM and capacitor structure device comprising: trenched capacitors in two twisted trenches through an insulating layer in a memory area of an integrated circuit wherein said two twisted trenches are mirror images of each other and wherein each capacitor in a first of said two twisted trenches is horizontally aligned with a capacitor in a second of said two twisted trenches to form pairs of capacitors wherein said pairs of capacitors are separated from each other horizontally by a first or a second distance wherein said first distance is greater than said second distance; a bit line contact in said memory area through said insulating layer to a bit line wherein said bit line contact lies between said two twisted trenches and in a horizontal line with one capacitor pair wherein said one capacitor pair has said first separation distance and adjacent capacitor pairs have said second separation distance; and first line metal contacts in a logic area of said integrated circuit; wherein said bit line contact and said first line metal contacts are no higher vertically than said trenched capacitors.
 34. A DRAM structure comprising: trenched capacitors in a trench through an insulating layer in a memory area, wherein each of said trenched capacitors comprises a bottom electrode lining an opening in said insulating layer, a capacitor dielectric layer disposed on said bottom electrode, and a top electrode disposed on said capacitor dielectric layer wherein an opening remains in said top electrode within said trench; and a conductive line disposed on said top electrodes and filling inside said opening and said trench continuously wherein said conductive line is no higher vertically than said top electrode.
 35. The DRAM structure according to claim 34, further comprising a bit line contact in said memory area through said insulating layer to a bit line.
 36. The DRAM structure according to claim 34, wherein said bit line contact is no higher vertically than said trenched capacitors.
 37. The DRAM structure according to claim 34, wherein said insulating layer is a laminated layer comprising a stop layer, an insulating oxide layer, a silicon carbide layer, and a low-K layer disposed sequentially over said memory area.
 38. The DRAM structure according to claim 37, wherein said trench is formed in said low-K layer and does not exceed said silicon carbide layer.
 39. The DRAM structure according to claim 37, wherein said bottom electrode is in contact with said stop layer.
 40. The DRAM structure according to claim 34, wherein said trench is twisted-shaped.
 41. A DRAM structure, comprising: trenched capacitors in two trenches through an insulating layer in a memory area; and two conductive lines filling said two trenches respectively and continuously in contact with said trenched capacitors; and a bit line contact in said memory area through said insulating layer to a bit line wherein said bit line contact lies between said two trenches; wherein said bit line contact is no higher vertically than said trench capacitors.
 42. The DRAM structure according to claim 41, wherein each of said trenched capacitors comprises a bottom electrode layer lining an opening in said insulating layer, a capacitor dielectric layer disposed on said bottom electrode, and a top electrode layer disposed on said capacitor dielectric layer.
 43. The DRAM structure according to claim 42, wherein said conductive lines are disposed on said top electrode layers and substantially filling inside said openings and said trenches respectively wherein said conductive lines are no higher vertically than said top electrode layers.
 44. The DRAM structure according to claim 42, wherein said insulating layer is a laminated layer comprising a stop layer, an insulating oxide layer, a silicon carbide layer, and a low-K layer, disposed sequentially over said memory area.
 45. The DRAM structure according to claim 44, wherein said trenches are formed in said low-K layer and do not exceed said silicon carbide layer.
 46. The DRAM structure according to claim 44, wherein said bottom electrodes contact said stop layer.
 47. The DRAM structure according to claim 41, wherein said trenches are twisted-shaped.
 48. An embedded DRAM and capacitor structure device, comprising: trenched capacitors in two trenches through an insulating layer in a memory area of an integrated circuit; a bit line contact in said memory area through said insulating layer to a bit line wherein said bit line contact lies between said two trenches; and first line metal contacts in a logic area of said integrated circuit; wherein said bit line contact and said first line metal contacts are no higher vertically than said trenched capacitors.
 49. The embedded DRAM and capacitor structure device according to claim 48, further comprising two conductive lines filling said two trenches respectively and continuously in contact with said trenched capacitors wherein said two conductive lines are no higher vertically than a top electrode of said trenched capacitors.
 50. The embedded DRAM and capacitor structure device according to claim 48, wherein said two trenches are twisted-shaped.
 51. The embedded DRAM and capacitor structure device according to claim 50, wherein said two twisted trenches are mirror images of each other.
 52. The embedded DRAM and capacitor structure device according to claim 50, wherein each capacitor in a first of said two twisted trenches is horizontally aligned with a capacitor in a second of said two twisted trenches to form pairs of capacitors wherein said pairs of capacitors are separated from each other horizontally by a first or a second distance wherein said first distance is greater than said second distance.
 53. The embedded DRAM and capacitor structure device according to claim 52, wherein said bit line contact is in a horizontal line with one capacitor pair wherein said one capacitor pair has said first separation distance and adjacent capacitor pairs have said second separation distance. 